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74LVC16374A; 74LVCH16374A
16-bit edge-triggered D-type flip-flop with 5 V tolerant inputs/outputs; 3-state
Rev. 07 -- 23 March 2010 Product data sheet
1. General description
The 74LVC16374A and 74LVCH16374A are 16-bit edge-triggered flip-flops featuring separate D-type inputs with bus hold (74LVCH16374A only) for each flip-flop and 3-state outputs for bus oriented applications. It consists of two sections of eight positive edge-triggered flip-flops. A clock input (nCP) and an output enable (nOE) are provided for each octal. The flip-flops will store the state of their individual D-inputs that meet the set-up and hold time requirements on the LOW-to-HIGH clock (CP) transition. When pin nOE is LOW, the contents of the flip-flops are available at the outputs. When pin nOE is HIGH, the outputs go to the high-impedance OFF-state. Operation of input nOE does not affect the state of the flip-flops. Inputs can be driven from either 3.3 V or 5 V devices. When disabled, up to 5.5 V can be applied to the outputs. These features allow the use of these devices in mixed 3.3 V and 5 V applications. Bus hold on data inputs eliminates the need for external pull-up resistors to hold unused inputs.
2. Features and benefits
5 V tolerant inputs/outputs for interfacing with 5 V logic Wide supply voltage range from 1.2 V to 3.6 V CMOS low power consumption Multibyte flow-through standard pin-out architecture Low inductance multiple supply pins for minimum noise and ground bounce Direct interface with TTL levels All data inputs have bus hold (74LVCH16374A only) High-impedance outputs when VCC = 0 V Complies with JEDEC standard JESD8-B/JESD36 ESD protection: HBM JESD22-A114F exceeds 2000 V CDM JESD22-C101D exceeds 1000 V Specified from -40 C to +85 C and -40 C to +125 C
NXP Semiconductors
74LVC16374A; 74LVCH16374A
16-bit edge-triggered D-type flip-flop; 5 V tolerant; 3-state
3. Ordering information
Table 1. Ordering information Package Temperature range 74LVC16374ADL 74LVCH16374ADL 74LVC16374ADGG 74LVCH16374ADGG 74LVC16374ABQ 74LVCH16374ABQ -40 C to +125 C -40 C to +125 C TSSOP48 -40 C to +125 C Name SSOP48 Description plastic shrink small outline package; 48 leads; body width 7.5 mm plastic thin shrink small outline package; 48 leads; body width 6.1 mm Version SOT370-1 SOT362-1 Type number
HXQFN60U plastic thermal enhanced extremely thin quad flat SOT1134-1 package; no leads; 60 terminals; UTLP based; body 4 x 6 x 0.5 mm
4. Functional diagram
1 1OE 48 1CP 24 2OE 25 2CP 1Q0 1Q1 1Q2 1Q3 1Q4 1Q5 1Q6 1Q7 2Q0 2Q1 2Q2 2Q3 2Q4 2Q5 2Q6 2Q7 1CP 48 2CP 25
001aaa253
EN1 C3 EN2 C4 3D 1 2 3 5 6 8 9 11 12 4D 2 13 14 16 17 19 20 22 23
001aaa254
1 1OE 47 46 44 43 41 40 38 37 36 35 33 32 30 29 27 26 1D0 1D1 1D2 1D3 1D4 1D5 1D6 1D7 2D0 2D1 2D2 2D3 2D4 2D5 2D6 2D7
24 2OE 2 3 5 6 8 9 11 12 13 14 16 17 19 20 22 23
1D0 1D1 1D2 1D3 1D4 1D5 1D6 1D7 2D0 2D1 2D2 2D3 2D4 2D5 2D6 2D7
47 46 44 43 41 40 38 37 36 35 33 32 30 29 27 26
1Q0 1Q1 1Q2 1Q3 1Q4 1Q5 1Q6 1Q7 2Q0 2Q1 2Q2 2Q3 2Q4 2Q5 2Q6 2Q7
Pin numbers are shown for SSOP48 and TSSOP48 packages only.
Pin numbers are shown for SSOP48 and TSSOP48 packages only.
Fig 1.
Logic symbol
Fig 2.
IEC logic symbol
74LVC_LVCH16374A_7
All information provided in this document is subject to legal disclaimers.
(c) NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 07 -- 23 March 2010
2 of 19
NXP Semiconductors
74LVC16374A; 74LVCH16374A
16-bit edge-triggered D-type flip-flop; 5 V tolerant; 3-state
1D0
D CP FF1
Q
1Q0
2D0
D CP FF2
Q
2Q0
1CP 1OE
2CP 2OE
to 7 other channels
to 7 other channels
001aaa255
Fig 3.
Logic diagram
VCC
data input
to internal circuit
mna705
Fig 4.
Bus hold circuit
74LVC_LVCH16374A_7
All information provided in this document is subject to legal disclaimers.
(c) NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 07 -- 23 March 2010
3 of 19
NXP Semiconductors
74LVC16374A; 74LVCH16374A
16-bit edge-triggered D-type flip-flop; 5 V tolerant; 3-state
5. Pinning information
5.1 Pinning
74LVC16374A 74LVCH16374A
1OE 1Q0 1Q1 GND 1Q2 1Q3 VCC 1Q4 1Q5
1 2 3 4 5 6 7 8 9
48 1CP 47 1D0 46 1D1 45 GND 44 1D2 43 1D3 42 VCC 41 1D4 40 1D5 39 GND 38 1D6 37 1D7 36 2D0 35 2D1 34 GND 33 2D2 32 2D3 31 VCC 30 2D4 29 2D5 28 GND 27 2D6 26 2D7 25 2CP
001aaa231
GND 10 1Q6 11 1Q7 12 2Q0 13 2Q1 14 GND 15 2Q2 16 2Q3 17 VCC 18 2Q4 19 2Q5 20 GND 21 2Q6 22 2Q7 23 2OE 24
Fig 5.
Pin configuration SOT370-1 (SSOP48) and SOT362-1 (TSSOP48)
74LVC_LVCH16374A_7
All information provided in this document is subject to legal disclaimers.
(c) NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 07 -- 23 March 2010
4 of 19
NXP Semiconductors
74LVC16374A; 74LVCH16374A
16-bit edge-triggered D-type flip-flop; 5 V tolerant; 3-state
terminal 1 index area
74LVC16374A 74LVCH16374A
D1 A32 A31 A30 A29 A28 A27 D4
A1
D5
B20
B19
B18
D8
A26
A2 B1 A3 B2 A4 B3 A5 B4 A6 B5 A7 B6 A8 B7 A9 GND(1) B11 B12 B13 B14 B15 B16 B17
A25
A24
A23
A22
A21
A20
A19
A18
A10
D6
B8
B9
B10
D7
A17
D2
A11
A12
A13
A14
A15
A16
D3
001aaj618
Transparent top view
(1) The die substrate is attached to this pad using conductive die attach material. It can not be used as a supply pin or input.
Fig 6.
Pin configuration SOT1134-1 (HXQFN60U)
74LVC_LVCH16374A_7
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(c) NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 07 -- 23 March 2010
5 of 19
NXP Semiconductors
74LVC16374A; 74LVCH16374A
16-bit edge-triggered D-type flip-flop; 5 V tolerant; 3-state
5.2 Pin description
Table 2. Symbol 1OE, 2OE GND VCC Pin description Pin SOT370-1 and SOT362-1 1, 24 4, 10, 15, 21, 28, 34, 39, 45 7, 18, 31, 42 SOT1134-1 A30, A13 A32, A3, A8, A11, A16, A19, A24, A27 A1, A10, A17, A26 B20, A31, D5, D1, A2, B2, B3, A5 A6, B5, B6, A9, D2, D6, A12, B8 output enable input (active LOW) ground (0 V) supply voltage data output data output Description
1Q0 to 1Q7 2, 3, 5, 6, 8, 9, 11, 12 2Q0 to 2Q7 13, 14, 16, 17, 19, 20, 22, 23 1D0 to 1D7 47, 46, 44, 43, 41, 40, 38, 37 2D0 to 2D7 36, 35, 33, 32, 30, 29, 27, 26 1CP, 2CP 48, 25
B18, A28, D8, D4, A25, B16, B15, A22 data input A21, B13, B12, A18, D3, D7, A15, B10 data input A29, A14 clock input
6. Functional description
Table 3. Function selection[1] Input nOE Load and read register Load register and disable outputs L L H H
[1] H = HIGH voltage level; h = HIGH voltage level one set-up time prior to the HIGH-to-LOW CP transition; L = LOW voltage level; l = LOW voltage level one set-up time prior to the HIGH-to-LOW CP transition; = LOW-to-HIGH transition; Z = high-impedance OFF-state.
Operating mode
Internal flip-flop nCP nDn l h l h L H L H
Output nQ0 to nQ7 L H Z Z
7. Limiting values
Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol VCC IIK VI IOK VO IO ICC IGND Tstg
74LVC_LVCH16374A_7
Parameter supply voltage input clamping current input voltage output clamping current output voltage output current supply current ground current storage temperature
Conditions VI < 0 V
[1]
Min -0.5 -50 -0.5 [2] [2]
Max +6.5 +6.5 50 VCC + 0.5 +6.5 50 100 +150
Unit V mA V mA V V mA mA mA C
6 of 19
VO > VCC or VO < 0 V output HIGH-or LOW-state output 3-state VO = 0 V to VCC
-0.5 -0.5 -100 -65
All information provided in this document is subject to legal disclaimers.
(c) NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 07 -- 23 March 2010
NXP Semiconductors
74LVC16374A; 74LVCH16374A
16-bit edge-triggered D-type flip-flop; 5 V tolerant; 3-state
Table 4. Limiting values ...continued In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol Ptot Parameter total power dissipation Conditions Tamb = -40 C to +125 C (T)SSOP48 package HXQFN60U package
[1] [2] [3] [4]
[3] [4]
Min -
Max 500 1000
Unit mW mW
The minimum input voltage ratings may be exceeded if the input current ratings are observed. The output voltage ratings may be exceeded if the output current ratings are observed. Above 60 C the value of Ptot derates linearly with 5.5 mW/K. Above 70 C the value of Ptot derates linearly with 1.8 mW/K.
8. Recommended operating conditions
Table 5. Symbol VCC VI VO Tamb t/V Recommended operating conditions Parameter supply voltage functional input voltage output voltage ambient temperature input transition rise and fall rate VCC = 1.65 V to 2.7 V VCC = 2.7 V to 3.6 V active mode power-down mode; VCC = 0 V Conditions Min 1.65 1.2 0 0 0 -40 0 0 Typ Max 3.6 5.5 VCC 5.5 +125 20 10 Unit V V V V V C ns/V ns/V
9. Static characteristics
Table 6. Static characteristics At recommended operating conditions. Voltages are referenced to GND (ground = 0 V). Symbol Parameter VIH VIL VOH HIGH-level input voltage Conditions VCC = 1.2 V VCC = 2.7 V to 3.6 V -40 C to +85 C Min VCC 2.0 VCC - 0.2 VCC - 0.5 VCC - 0.6 VCC - 0.8 Typ[1] Max GND 0.8 -40 C to +125 C Min VCC 2.0 VCC - 0.3 VCC - 0.65 VCC - 0.75 VCC - 1.0 Max GND 0.8 V V V V V V V V Unit
LOW-level input VCC = 1.2 V voltage VCC = 2.7 V to 3.6 V HIGH-level output voltage VI = VIH or VIL IO = -100 A; VCC = 2.7 V to 3.6 V IO = -12 mA; VCC = 2.7 V IO = -18 mA; VCC = 3.0 V IO = -24 mA; VCC = 3.0 V
74LVC_LVCH16374A_7
All information provided in this document is subject to legal disclaimers.
(c) NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 07 -- 23 March 2010
7 of 19
NXP Semiconductors
74LVC16374A; 74LVCH16374A
16-bit edge-triggered D-type flip-flop; 5 V tolerant; 3-state
Table 6. Static characteristics ...continued At recommended operating conditions. Voltages are referenced to GND (ground = 0 V). Symbol Parameter VOL LOW-level output voltage Conditions VI = VIH or VIL IO = 100 A; VCC = 2.7 V to 3.6 V IO = 12 mA; VCC = 2.7 V IO = 24 mA; VCC = 3.0 V II IOZ IOFF ICC ICC input leakage current OFF-state output current VCC = 3.6 V; VI = 5.5 V or GND VI = VIH or VIL; VCC = 3.6 V; VO = 5.5 V or GND;
[2]
-40 C to +85 C Min [3]
-40 C to +125 C Min Max 0.3 0.6 0.8 20 20 20 80 5000
Unit
Typ[1] 0.1 0.1 0.1 0.1 5
Max 0.2 0.4 0.55 5 5 10 20 500
V V V A A A A A
[2]
power-off VCC = 0 V; VI or VO = 5.5 V leakage current supply current additional supply current input capacitance bus hold LOW current bus hold HIGH current bus hold LOW overdrive current bus hold HIGH overdrive current VCC = 3.6 V; VI = VCC or GND; IO = 0 A per input pin; VCC = 2.7 V to 3.6 V; VI = VCC - 0.6 V; IO = 0 A VCC = 0 V to 3.6 V; VI = GND to VCC VCC = 3.0 V; VI = 0.8 V VCC = 3.0 V; VI = 2.0 V VCC = 3.6 V
[4][5]
-
CI IBHL IBHH IBHLO
75 -75 500
5.0 -
-
60 -60 500
-
pF A A A
[4][5]
[4][6]
IBHHO
VCC = 3.6 V
[4][6]
-500
-
-
-500
-
A
[1] [2] [3] [4] [5] [6]
All typical values are measured at VCC = 3.3 V and Tamb = 25 C. The bus hold circuit is switched off when VI > VCC allowing 5.5 V on the input pin. For non bus hold parts only (74LVC16374A). Valid for data inputs only. Control inputs do not have a bus hold circuit. The specified sustaining current at the data input holds the input below the specified VI level. The specified overdrive current at the data input forces the data input to the opposite logic input state.
74LVC_LVCH16374A_7
All information provided in this document is subject to legal disclaimers.
(c) NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 07 -- 23 March 2010
8 of 19
NXP Semiconductors
74LVC16374A; 74LVCH16374A
16-bit edge-triggered D-type flip-flop; 5 V tolerant; 3-state
10. Dynamic characteristics
Table 7. Dynamic characteristics Voltages are referenced to GND (ground = 0 V). For test circuit see Figure 10. Symbol Parameter tpd propagation delay Conditions nCP to nQn; see Figure 7 VCC = 1.2 V VCC = 2.7 V VCC = 3.0 V to 3.6 V ten enable time nOE to nQn; see Figure 9 VCC = 1.2 V VCC = 2.7 V VCC = 3.0 V to 3.6 V tdis disable time nOE to nQn; see Figure 7 VCC = 1.2 V VCC = 2.7 V VCC = 3.0 V to 3.6 V tW pulse width nCP HIGH; see Figure 7 VCC = 1.2 V VCC = 2.7 V VCC = 3.0 V to 3.6 V tsu set-up time nDn to nCP; see Figure 8 VCC = 1.2 V VCC = 2.7 V VCC = 3.0 V to 3.6 V th hold time nDn to nCP; see Figure 8 VCC = 1.2 V VCC = 2.7 V VCC = 3.0 V to 3.6 V fmax maximum frequency see Figure 7 VCC = 2.7 V VCC = 3.0 V to 3.6 V tsk(o) output skew time VCC = 3.0 V to 3.6 V
[3] [2] [2] [2]
-40 C to +85 C Min 1.5 1.5 1.5 1.0 1.5 1.5 3.0 3.0 1.9 1.9 1.1 1.5 80 100 Typ[1] 14 3.4 20 3.5 12 3.9 1.5 0.3 -0.3 150 Max 6.0 5.4 6.0 5.2 5.1 4.9 1.0
-40 C to +125 C Unit Min 1.5 1.5 1.5 1.0 1.5 1.5 3.0 3.0 1.9 1.9 1.1 1.5 80 100 Max 7.5 7.0 7.5 6.5 6.5 6.5 1.5 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns MHz MHz ns
[1] [2]
Typical values are measured at Tamb = 25 C and VCC = 1.2 V, 2.7 V, and 3.3 V respectively. tpd is the same as tPLH and tPHL. ten is the same as tPZL and tPZH. tdis is the same as tPLZ and tPHZ.
[3]
Skew between any two outputs of the same package switching in the same direction. This parameter is guaranteed by design.
74LVC_LVCH16374A_7
All information provided in this document is subject to legal disclaimers.
(c) NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 07 -- 23 March 2010
9 of 19
NXP Semiconductors
74LVC16374A; 74LVCH16374A
16-bit edge-triggered D-type flip-flop; 5 V tolerant; 3-state
11. Waveforms
1/fmax VI nCP input GND tW t PHL VOH nQn output VOL VM
001aaa256
VM
VM
t PLH
Measurement points are given in Table 8. VOL and VOH are the typical output voltage levels that occur with the output load.
Fig 7.
Clock (nCP) to output (nQn) propagation delays, clock pulse width, and the maximum frequency
VI nCP input GND t su th VI nDn input GND VM t su th VM
VOH nQn output VOL
001aaa257
VM
Measurement points are given in Table 8. The shaded areas indicate when the input is permitted to change for predictable performance. VOL and VOH are the typical output voltage levels that occur with the output load.
Fig 8.
Data set-up and hold times for the nDn input to the nCP input
74LVC_LVCH16374A_7
All information provided in this document is subject to legal disclaimers.
(c) NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 07 -- 23 March 2010
10 of 19
NXP Semiconductors
74LVC16374A; 74LVCH16374A
16-bit edge-triggered D-type flip-flop; 5 V tolerant; 3-state
VI nOE input GND tPLZ VCC output LOW-to-OFF OFF-to-LOW VOL tPHZ VOH output HIGH-to-OFF OFF-to-HIGH GND outputs enabled VY VM VM VX tPZH tPZL VM
outputs disabled
outputs enabled
mna362
Measurement points are given in Table 8. VOL and VOH are the typical output voltage levels that occur with the output load.
Fig 9. Table 8. VCC 1.2 V 2.7 V
3-state enable and disable times Measurement points Input VI VCC 2.7 V 2.7 V VM 0.5 x VCC 1.5 V 1.5 V Output VM 0.5 x VCC 1.5 V 1.5 V VX VOL + 0.1 V VOL + 0.3 V VOL + 0.3 V VY VOH - 0.1 V VOH - 0.3 V VOH - 0.3 V
Supply voltage
3.0 V to 3.6 V
74LVC_LVCH16374A_7
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(c) NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 07 -- 23 March 2010
11 of 19
NXP Semiconductors
74LVC16374A; 74LVCH16374A
16-bit edge-triggered D-type flip-flop; 5 V tolerant; 3-state
VI negative pulse 0V
tW 90 % VM 10 % tf tr tr tf 90 % VM 10 % tW
VEXT VCC VI VO
RL
VM
VI positive pulse 0V
VM
G
RT
DUT
CL RL
001aae331
Test data is given in Table 9. Definitions for test circuit: RL = Load resistance. CL = Load capacitance including jig and probe capacitance. RT = Termination resistance should be equal to output impedance Zo of the pulse generator. VEXT = External voltage for measuring switching times.
Fig 10. Test circuit for measuring switching times Table 9. Test data Input VI 1.2 V 2.7 V 3.0 V to 3.6 V
[1]
Supply voltage
Load tr, tf 2.5 ns 2.5 ns 2.5 ns CL 50 pF 50 pF 50 pF RL 500 [1] 500 500
VEXT tPLH, tPHL open open open tPLZ, tPZL 2 x VCC 2 x VCC 2 x VCC tPHZ, tPZH GND GND GND
VCC 2.7 V 2.7 V
The circuit performs better when RL = 1 k.
74LVC_LVCH16374A_7
All information provided in this document is subject to legal disclaimers.
(c) NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 07 -- 23 March 2010
12 of 19
NXP Semiconductors
74LVC16374A; 74LVCH16374A
16-bit edge-triggered D-type flip-flop; 5 V tolerant; 3-state
12. Package outline
SSOP48: plastic shrink small outline package; 48 leads; body width 7.5 mm SOT370-1
D
E
A
X
c y HE vM A
Z
48 25
Q A2 A1 (A 3) Lp
1 24
A
pin 1 index L wM detail X
e
bp
0
5 scale
10 mm
DIMENSIONS (mm are the original dimensions) UNIT mm Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT370-1 REFERENCES IEC JEDEC MO-118 JEITA EUROPEAN PROJECTION A max. 2.8 A1 0.4 0.2 A2 2.35 2.20 A3 0.25 bp 0.3 0.2 c 0.22 0.13 D (1) 16.00 15.75 E (1) 7.6 7.4 e 0.635 HE 10.4 10.1 L 1.4 Lp 1.0 0.6 Q 1.2 1.0 v 0.25 w 0.18 y 0.1 Z (1) 0.85 0.40 8 o 0
o
ISSUE DATE 99-12-27 03-02-19
Fig 11. Package outline SOT370-1 (SSOP48)
74LVC_LVCH16374A_7 All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 07 -- 23 March 2010
13 of 19
NXP Semiconductors
74LVC16374A; 74LVCH16374A
16-bit edge-triggered D-type flip-flop; 5 V tolerant; 3-state
TSSOP48: plastic thin shrink small outline package; 48 leads; body width 6.1 mm
SOT362-1
D
E
A X
c y HE vMA
Z
48
25
Q A2 A1 pin 1 index Lp L (A 3) A
1
e bp
24
wM
detail X
0
2.5 scale
5 mm
DIMENSIONS (mm are the original dimensions). UNIT mm A max. 1.2 A1 0.15 0.05 A2 1.05 0.85 A3 0.25 bp 0.28 0.17 c 0.2 0.1 D (1) 12.6 12.4 E (2) 6.2 6.0 e 0.5 HE 8.3 7.9 L 1 Lp 0.8 0.4 Q 0.50 0.35 v 0.25 w 0.08 y 0.1 Z 0.8 0.4 8 o 0
o
Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT362-1 REFERENCES IEC JEDEC MO-153 JEITA EUROPEAN PROJECTION
ISSUE DATE 99-12-27 03-02-19
Fig 12. Package outline SOT362-1 (TSSOP48)
74LVC_LVCH16374A_7 All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 07 -- 23 March 2010
14 of 19
NXP Semiconductors
74LVC16374A; 74LVCH16374A
16-bit edge-triggered D-type flip-flop; 5 V tolerant; 3-state
HXQFN60U: plastic thermal enhanced extremely thin quad flat package; no leads; 60 terminals; UTLP based; body 4 x 6 x 0.5 mm
D B A
SOT1134-1
terminal 1 index area
E
A
A1
detail X
e2 e1 1/2 e v w L1 CAB C D2 D6 A10 eR B7 e b A11 B8 B10 A16 D7 A17 B11 D3 v w CAB C y1 C C y
L
e
Eh 1/2 e B1 A1 terminal 1 index area D5 D1 B20 A32 Dh k 0 Dimensions Unit mm A A1 b D 4.1 4.0 3.9 Dh 1.90 1.85 1.80 E 6.1 6.0 5.9 Eh 3.90 3.85 3.80 e 0.5 e1 1 2.5 scale e2 2.5 B18 A27 D8 D4 B17 A26
e3
e4
X
5 mm
e3 3
e4 4.5
eR 0.5
k
L
L1 0.125 0.075 0.025
v
w
y
y1 0.1
sot1134-1_po
max 0.50 0.05 0.35 nom 0.48 0.02 0.30 min 0.46 0.00 0.25
0.25 0.35 0.20 0.30 0.15 0.25
0.07 0.05 0.08
Outline version SOT1134-1
References IEC --JEDEC --JEITA ---
European projection
Issue date 08-12-17 09-01-22
Fig 13. Package outline SOT1134-1 (HXQFN60U)
74LVC_LVCH16374A_7 All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 07 -- 23 March 2010
15 of 19
NXP Semiconductors
74LVC16374A; 74LVCH16374A
16-bit edge-triggered D-type flip-flop; 5 V tolerant; 3-state
13. Abbreviations
Table 10. Acronym CDM DUT ESD HBM TTL Abbreviations Description Charged Device Model Device Under Test ElectroStatic Discharge Human Body Model Transistor-Transistor Logic
14. Revision history
Table 11. Revision history Release date 20100323 Data sheet status Product data sheet Change notice Supersedes 74LVC_LVCH16374A_6 Document ID 74LVC_LVCH16374A_7 Modifications: 74LVC_LVCH16374A_6 Modifications:
* * * *
74LVC16374ABQ and 74LVCH16374ABQ changed from HUQFN60U (SOT1025-1) to HXQFN60U (SOT1134-1) package. Product data sheet 74LVC_LVCH16374A_5 The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors. Legal texts have been adapted to the new company name where appropriate. Added: type numbers 74LVC16374ABQ and 74LVCH16374ABQ (HUQFN60U package). Product specification Product specification Product specification Product specification 74LVC_H16374A_4 74LVC16374A_ 74LVCH16374A_3 74LVC16374A_2 74LVC16374A_1 -
20090212
74LVC_LVCH16374A_5 74LVC_H16374A_4 74LVC16374A_ 74LVCH16374A_3 74LVC16374A_2 74LVC16374A_1
20031212 19980317 19980317 19970822 -
74LVC_LVCH16374A_7
All information provided in this document is subject to legal disclaimers.
(c) NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 07 -- 23 March 2010
16 of 19
NXP Semiconductors
74LVC16374A; 74LVCH16374A
16-bit edge-triggered D-type flip-flop; 5 V tolerant; 3-state
15. Legal information
15.1 Data sheet status
Document status[1][2] Objective [short] data sheet Preliminary [short] data sheet Product [short] data sheet
[1] [2] [3]
Product status[3] Development Qualification Production
Definition This document contains data from the objective specification for product development. This document contains data from the preliminary specification. This document contains the product specification.
Please consult the most recently issued document before initiating or completing a design. The term `short data sheet' is explained in section "Definitions". The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com.
15.2 Definitions
Draft -- The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet -- A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. Product specification -- The information and data provided in a Product data sheet shall define the specification of the product as agreed between NXP Semiconductors and its customer, unless NXP Semiconductors and customer have explicitly agreed otherwise in writing. In no event however, shall an agreement be valid in which the NXP Semiconductors product is deemed to offer functions and qualities beyond those described in the Product data sheet.
suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer's own risk. Applications -- Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on a weakness or default in the customer application/use or the application/use of customer's third party customer(s) (hereinafter both referred to as "Application"). It is customer's sole responsibility to check whether the NXP Semiconductors product is suitable and fit for the Application planned. Customer has to do all necessary testing for the Application in order to avoid a default of the Application and the product. NXP Semiconductors does not accept any liability in this respect. Limiting values -- Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. Terms and conditions of commercial sale -- NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. NXP Semiconductors hereby expressly objects to applying the customer's general terms and conditions with regard to the purchase of NXP Semiconductors products by customer. No offer to sell or license -- Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Export control -- This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from national authorities.
15.3 Disclaimers
Limited warranty and liability -- Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. Notwithstanding any damages that customer might incur for any reason whatsoever, NXP Semiconductors' aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of NXP Semiconductors. Right to make changes -- NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use in automotive applications -- This NXP Semiconductors product has been qualified for use in automotive applications. The product is not designed, authorized or warranted to be
74LVC_LVCH16374A_7
15.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners.
All information provided in this document is subject to legal disclaimers.
(c) NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 07 -- 23 March 2010
17 of 19
NXP Semiconductors
74LVC16374A; 74LVCH16374A
16-bit edge-triggered D-type flip-flop; 5 V tolerant; 3-state
16. Contact information
For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com
74LVC_LVCH16374A_7
All information provided in this document is subject to legal disclaimers.
(c) NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 07 -- 23 March 2010
18 of 19
NXP Semiconductors
74LVC16374A; 74LVCH16374A
16-bit edge-triggered D-type flip-flop; 5 V tolerant; 3-state
17. Contents
1 2 3 4 5 5.1 5.2 6 7 8 9 10 11 12 13 14 15 15.1 15.2 15.3 15.4 16 17 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 Pinning information . . . . . . . . . . . . . . . . . . . . . . 4 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 6 Functional description . . . . . . . . . . . . . . . . . . . 6 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 6 Recommended operating conditions. . . . . . . . 7 Static characteristics. . . . . . . . . . . . . . . . . . . . . 7 Dynamic characteristics . . . . . . . . . . . . . . . . . . 9 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 13 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 16 Legal information. . . . . . . . . . . . . . . . . . . . . . . 17 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 17 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Contact information. . . . . . . . . . . . . . . . . . . . . 18 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Please be aware that important notices concerning this document and the product(s) described herein, have been included in section `Legal information'.
(c) NXP B.V. 2010.
All rights reserved.
For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 23 March 2010 Document identifier: 74LVC_LVCH16374A_7

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